The present invention pertains in general to a Gigabit Media Independent Interface (GMII) with a reduced pin count interface for the physical layer of devices and, more particularly, to the timing considerations for transferring data between the Physical Layers Devices (PHY) and the Media Access Controller (MAC).
In high speed ethernet controllers, such as the gigabit ethernet controllers, data is transferred at relatively high rates. In one instantiation, the driver/receiver circuitry is contained within a physical layer device (PHY) with media access control being contained within a Media Access Control (MAC) block. Data is received by the PHY device from the transmission medium and then transmitted to the MAC for a receive operation. During a transmit operation, data is transferred from the MAC to the PHY layer and the PHY layer then transmits the data onto the transmission medium. Each of the MAC and PHY blocks have independent clocks such that a data clock is always transmitted with the data. Due to the high data rate in the gigabit controller, some timing compensation is required between the chips to insure that the clock and data are properly aligned at the receiver. The reason for this is that the clock edge of the data clock in the transmitter is utilized to generate data and then is also utilized at the opposite end of the transmission line in the receiver to sample the data. To insure that the sampling is done only during xe2x80x9cdata validxe2x80x9d windows, the clock is delayed with respect to the data. The typical way that this is done at present is to utilize trombone section transmission lines between the PHY and MAC devices which will introduce a predetermined amount of propagation delay into the signal path. However, this requires the board designer on which the MAC and PHY chips reside to handle the propagation delay problem. Additionally, this requires more board space to accommodate this layout.
The present invention disclosed and claimed herein, in one aspect thereof, comprises a data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. A first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time substantially equal to one-half clock cycle of the internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.